1. Field of the Invention
The present invention generally relates to a semiconductor wafer and a method of forming the same. More specifically, the present invention relates to a semiconductor wafer including a cracking stopper structure and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2007-315051, filed Dec. 5, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, most of the semiconductor devices may include a semiconductor substrate, a device layer, and a multi-level interconnection layer. The device layer may be disposed over the semiconductor substrate. The device layer may include semiconductor elements such as transistors. The multi-level interconnection layer may be disposed over the device layer. The multi-level interconnection layer may include interconnections or wirings at plural different levels. In recent years, the multi-level interconnection layer may often have a damascene structure. In some cases, the multi-level interconnection layer with the damascene structure may include plural inter-layer insulators, barrier layers, metal interconnections, and via contacts. At least one of the inter-layer insulators other than the upper most inter-layer insulator may include a lower dielectric region that has a dielectric constant of less than 3.9. The lower dielectric region may be positioned at a level where the damascene structure is used. The barrier layers are disposed between the plural inter-layer insulators. The metal interconnections may typically be made of Cu. The metal interconnections may be formed in grooves of the inter-layer insulators. The via contacts may extend in the inter-layer insulators and between the metal interconnections at different levels. Typically, the via contacts extend in a direction vertical to the surface of the semiconductor substrate. In some cases, the inter-layer insulator may be made of, but not limited to, SiCO which is different from silicon oxide in that some Si—O bonding of silicon oxide is substituted with methyl groups. In some cases, the barrier layer may be made of, but not limited to, SiCN.
Adhesiveness is low between the SiCO film as the inter-layer insulator and the SiCN film as the barrier layer. The low adhesiveness between the inter-layer insulator and the barrier layer may cause that the inter-layer insulator and the barrier layer are peeled from each other in the process of dicing the semiconductor wafer, thereby deteriorating the moisture resistance of the semiconductor chip. A countermeasure to the possible peeling between the inter-layer insulator and the barrier layer is to provide a cracking stopper to the wafer. The cracking stopper is a groove which extends along the circumference of the semiconductor chip. In some cases, the cracking stopper groove has such a depth that the bottom of the cracking stopper groove is just above the first level interconnection.
The semiconductor manufacturing processes may include a process for forming openings in an uppermost passivation film, wherein the openings are positioned directly over bonding pads. The process for forming the openings in the uppermost passivation film can be carried out by an etching process using an etching mask that is disposed over the uppermost passivation film. This etching mask is also used to form the cracking stopper groove. Namely, the openings and the cracking stopper groove are formed in the same etching process. Such a wide width of the groove as a few micrometers will be necessary to obtain a deep depth of the groove by the single etching process. Increase of the width of the groove will decrease the effective or useful area for the chips in a single wafer, thereby decreasing the number of chips obtained from the single wafer.
If it is intended to reduce the number of used masks to the minimum number, a mask has to be disposed on the passivation film, thereby causing a residual on the dicing line, wherein the residual is of the material such as polyimide for the passivation film. The residual of the material such as polyimide will shorten the lifetime of a dicing saw.
Japanese Unexamined Patent Application, First Publication, No. 2005-260059 discloses that grooves extend on dicing regions entirely. Namely, the dicing regions are entirely etched. This method makes it unnecessary to use the additional mask over the passivation film. The dicing regions may often include a pattern of terminals for wafer test. The dicing regions are entirely etched, while the pattern of terminals is also etched, thereby making it difficult or impossible to conduct the wafer test.
Japanese Unexamined Patent Application, First Publication, No. 2006-516824 discloses that an interconnection portion of the dicing region is removed by a wet etching process to selectively form a groove structure, while a pattern of terminals for wafer test is also removed.